The present invention relates to a method of controlling the transfer of a variety of information such as instruction information or data information between a memory or a peripheral circuit and a data processor, and a peripheral circuit, a data processor and a data processing system using the method, and, more particularly, to a technique which is especially effective if applied to the control technique of the data transfer between the data processor and a memory. Incidentally, the data processor in the present Specification will cover the general concept of a CPU (i.e., Central Processing Unit), a microprocessor, a microcomputer, a single-chip microcomputer, a digital-signal processor or a direct memory access controller.
Some RISC processors of the prior art include one or more cache memories in a chip from the point of view of performance, cost, manufacture process and technical level of the LSI. Such a CPU is connected with a number of memories and input/output) circuits on a circuit board to construct a system. It is usual to use an operation clock (or system clock) as a reference to the operation of the system. Usually, the peripheral circuits such as the memories and the input/output circuits to constitute the system are individually given different functions and characteristics to have individually different operating procedures, response times or operating speeds. It is needless to say that the CPU interfaces owned by the memories and the input/output circuits are frequently different from one another although they have some similarity in the functions or timings.
As to the differences in such functions, operating speeds and interface specifications, memory controllers are used for the memories, and I/O controllers are used for the input/output circuits. These controllers have functions, as roughly divided into the following two points.
The first function is to inform the memories and the input/output circuits of which memory or input/output circuit is selected by the CPU, and initiates a data transfer. This function can be regarded as the so-called xe2x80x9cchip selectionxe2x80x9d or xe2x80x9cchip enable controlxe2x80x9d. For example, logic operations between the signals indicating the kinds of addressing and access are carried out to produce pulses or level signals by using an operation clock or the like thereby to activate only the memory selected or the signal connected with the input/output circuit.
The second function is to count the operation clocks by a counter thereby to produce a signal demanding the CPU for an extension of the access period at the unit of the operation clock for the wait or ready operation. Under to the rule of confirming the signal for each operation clock by the CPU, the difference in the timing or the operation speed between the CPU and the memory or the peripheral circuit is absorbed to realize the data transfer without fail. This function is the so-called xe2x80x9cwait state control functionxe2x80x9d.
However, we have revealed that the aforementioned wait state function by the controller has the following problems.
(1) Since the duration of the data transfer time to be extended by the wait state is always determined at the operation clock unit of the system, it is impossible to sufficiently extract the performance intrinsic to the memory or peripheral circuit. Moreover, it is substantially impossible to design the system by using the performance, which is based upon the design data submitted by the maker/seller as to the memory or the input/output circuit, in the limit state. Since a certain operation margin is considered, a data transfer involves idle time in most cases so that the data transfer efficiency on the data bus decreases. This problem applies not only to the case in which the system is constructed on a circuit board, i.e., in which the connections between the memories or the input/output circuits and the CPU are made through the buses on the board, but also to the case in which the CPU and the memories are formed over a common semiconductor chip. Specifically, if an optimum design were to made considering the electric characteristics and the arrangement of circuit elements, the controllers and the memories could effect the data transfer efficiently to the operation clock of the controllers. In the actual circuit design, however, a delicate timing has to be made in the chip although not easy, while considering the characteristics of the individual logic circuit blocks.
(2) The aforementioned wait state control takes serious troubles because the designer has to design the system for the individual memories or input/output circuits, if in plurality, due to the differences in the functions (including the protocol) and performances.
(3) The circuit portions required for the wait state control have to cover the sets of memories and input/output circuits, thus causing difficulties in the high speed, the small size and the low prices such as the complicatedness of the system, the increase in the part number or the increase in the load upon the signal line.
(4) As has been described in the aforementioned problem (1), the wait state control cannot sufficiently extract the performances intrinsic to the memories and the peripheral circuits so that it limits the speed-up of the operations. In order to eliminate this limit, therefore, all or the highly efficient memories or input/output circuits could be connected without the wait state control. If, however, the operation clock of the controller is suppressed according to the characteristics such as the operation speed of the memories and the input/output circuits, the controller such as the CPU has a tendency to have its operation clock speeded up to drop the value of the system. If, on the contrary, a fast memory or input/output circuit is to be used in conformity to the operation clock of the controller, an extremely high rise is caused in the system price.
Thus, the system of the prior art for producing the timing of the data transfer between the CPU and the peripheral circuit from the operation clock of the CPU or the system cannot realize the data transfer which can sufficiently exploit the intrinsic performance of the peripheral circuit such as the memory. Specifically, we have thought it difficult to desire a basic development to a high speed if the CPU and the peripheral circuit are connected by the wait state control function which stresses the reliable operation by returning the wait signal to the CPU at a timing of integer times as high as that of the operation clock on the basis of the characteristics of the peripheral circuit.
An object of the present invention is to provide a technique which is enabled to effect a data transfer by sufficiently exhibiting the intrinsic characteristics owned by a peripheral circuit such as a memory.
Another object of the present invention is to provide a peripheral circuit for producing a timing of the data transfer according to its own characteristics.
A further object of the present invention is to provide a data processor capable of transferring data efficiently with such peripheral circuit.
A further object of the present invention is to provide a data processing system capable of transferring data fast with the data processor by sufficiently exhibiting the intrinsic characteristics owned by the peripheral circuit such as the memory.
The aforementioned and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
A representative of the invention to be disclosed herein will be briefly described in the following.
Specifically, as represented in FIG. 1, a memory (1) acting as a peripheral circuit performs its internal operation in accordance with access requests (200, 201 and 202) from a CPU (2) exemplifying the data processor, and in synchronism with the output signal of a self-excited oscillator (102) incorporated therein; and outputs a response requests (103) to the data processor in synchronism with that internal operation in response to the access requests.
The data processor sends an access request to a desired peripheral circuit; and transfers data to or from the peripheral circuit depending on the type of the access request in synchronism with a response request received from the peripheral circuit.
The control of the data transfer between the data processor and the peripheral circuit comprises the steps of sending an access request to the peripheral circuit from the data processor; allowing the peripheral circuit to perform its internal operation according to the access request in synchronism with the output signal of a self-excited oscillator incorporated therein; sending a response to the peripheral circuit from the data processor in synchronism with its internal operation in response to the access request; and transferring data to or from the data processor depending on the type of the access request in synchronism with said response request.
In order to realize the aforementioned means with the minimum number of circuits to be added to the construction of the existing data processor or peripheral circuit, the access requests can contain the information (200 and 201) for indicating that the peripheral circuit is selected as the object to be accessed and the data transfer direction, and the response request can contain the signal (103) to be changed in synchronism with the internal operation of the peripheral circuit.
In order to construct the peripheral circuit having the aforementioned functions relatively simply, as representatively shown in FIG. 5, the peripheral circuit includes a cycle timing generator (1010) for producing an access cycle signal (1013) of the internal operation in response to the access request from the data processor and on the basis of an output signal of the self-excited oscillator (102); an external terminal (AC) for outputting the access cycle signal as the response request to the outside; and an internal timing generator (1011) for producing an internal operation timing signal in synchronism with the access cycle signal (103).
In case such peripheral circuit is constructed as a burst readable memory (capable of reading a continuous data of a plurality of words), there may be added a counter (or burst counter) (105) for counting the number of continuous data read words from the memory cell array on the basis of the change in the access cycle signal to stop the oscillations of the self-excited oscillator when the counted result reaches a predetermined count value, as representatively shown in FIG. 6. At this time, in order to set the number of continuous data read words programmably, the counter is equipped with a parameter register (1051) for latching the predetermined count value presettably from the outside, as representatively shown in FIG. 12. This parameter register can be positioned such that in case the counter has storage stages corresponding to its bit count, the memory stages are used as a substantial parameter register in a presettable manner.
In order to transfer data at different transfer rates quickly and efficiently between the internal unit and the outside, the data processor having the aforementioned functions is equipped, as representatively shown in FIG. 8, with a buffer memory (206) which includes: a asynchronous port (2064) for writing/reading on the basis of the response request; and a synchronous port (2065) for writing/reading in synchronism with the internal operation clock. The synchronous port of the buffer memory is connected as the internal unit to an arithmetic unit or register, and the asynchronous port of the buffer memory is connected with an input/output buffer circuit (205) to be interfaced with the outside. At this time, in order that the data transferred from the peripheral circuit to the buffer memory may be quickly used for the operation of an internal unit (204), the buffer memory may be equipped with a counter circuit (2066) for counting the number of continuous read accesses, which are sent to the peripheral circuit from the access control circuit, in terms of the number of changes in the response request, so that the resultant detection result may be fed as the information meaning the complete of the read data acquisition by said access request (i.e., the output information of an AND gate 2063R5, as representatively shown in FIG. 9) to the central processing unit. The buffer memory should not be limited to a perfect dual port but may be used as an apparent dual port for operating a unit-port buffer memory in a time sharing manner.
When the data processor is interfaced with a plurality of peripheral circuits of different kinds, one input terminal of the data processor for response request is connected through an OR gate or a wired OR so that it may be shared among the output terminals of each peripheral circuit for the response request, as representatively shown in FIG. 14.
In order that mutually identical peripheral circuits having a multi-bit input/output function of xc2xdn bits for the number of bits of the data bus may be interfaced with the data processor, the data processor may be provided with a plurality of sets of buffer memories (206U and 206L) each having: an asynchronous port for writing/reading in response to the response request; and a synchronous port for writing/reading in synchronism with the internal operation clock, as representatively shown in FIG. 13.
According to the means described above, the peripheral circuit is operated synchronously with the output signal of the self-excited oscillator intrinsic thereto but asynchronously from the operation clock signal of the data processor requesting access to the peripheral circuit. In this relation, the mutual interface of data is realized by the mutually equivalent access requests and the response requests for the former. As a result, the time period for the series of data transfer, which as been limited to integer times as high as that of the fundamental operation clock of the data processor of the prior art, is determined according to the clock cycle of the response request depending upon the intrinsic self-excited oscillation frequency which is produced according to the characteristics such as the operation speed of the peripheral circuit such as the memory. As a result, the data transfer can be easily realized for the individual characteristic limit time periods of the peripheral circuit and the data processor. In other words, it is possible to reduce the spare time period which has been established for synchronization with the operation clock of the data processor, as has been troubled in the prior art. Moreover, the wait state control circuit for the interface between the data processor and each peripheral circuit can be dispensed with to simplify the circuit connecting means.
The data processor equipped on-chip with the buffer memory to be interfaced with the peripheral circuit can internally absorb the difference in the data transfer rate between the internal unit of the data processor and the outside to require no sequential wait time for reading/writing the data in response to the access request.